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general description the MAX16993 power-management integrated cir - cuit (pmic) is a 2.1mhz, multichannel, dc-dc con - verter designed for automotive applications. the device integrates three supplies in a small footprint. the device includes one high-voltage step-down controller (out1) designed to run directly from a car battery and two low- voltage step-down converters (out2/out3) cascaded from out1. under no-load conditions, the MAX16993 consumes only 30a of quiescent current, making it ideal for automotive applications. the high-voltage synchronous step-down dc-dc controller (out1) operates from a voltage up to 36v continuous and is protected from load-dump transients up to 42v. there is a pin-selectable frequency option of either 2.1mhz or a factory- set frequency for 1.05mhz, 525khz, 420khz, or 350khz. the low-voltage, synchronous step-down dc-dc converters run directly from out1 and can supply output currents up to 3a. the device provides a spread-spectrum enable input (ssen) to provide quick improvement in electromagnetic interference when needed. there is also a sync i/o for providing either an input to synchronize to an external clock source or an out - put of the internally generated clock (see the selector guide ). the device includes overtemperature shutdown and overcur - rent limiting. the device also includes individual reset_ outputs and individual enable inputs. the individual reset_ outputs provide voltage monitoring for all output channels. the MAX16993 is available in a 32-pin side-wettable tqfn- ep package and is specified for operation over the -40c to +125c automotive temperature range. applications automotive industrial features high-voltage dc-dc controller ? 3.5v to 36v operating supply voltage ? 42v load-dump protection ? output voltage: pin selectable, fixed or resistor-divider adjustable ? 350khz to 2.1mhz operation ? 30a quiescent current with dc-dc controller enabled dual high-efficiency 2.1mhz dc-dc converters ? run directly from out1 ? 3a integrated fets ? 0.8v to 3.95v output voltage ? fixed or resistor-divider-adjustable output voltage ? 180 out-of-phase operation individual enable inputs individual reset_ outputs thermal-warning indication output forced-pwm and skip modes overtemperature and short-circuit protection 32-pin (5mm x 5mm x 0.8mm) side-wettable tqfn-ep -40c to +125c operating temperature range 19-6684; rev 0; 5/13 ordering information and selector guide appear at end of data sheet. evaluation kit available MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters
maxim integrated 2 electrical characteristics (v sup = 14v, v pv1 = v bias , v pv2 = v pv3 = v out1 ; t a = t j = -40 c to +125 c, unless otherwise noted. typical values are at t a = +25 c under normal conditions, unless otherwise noted.) (note 2) note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) side-wettable tqfn junction-to-ambient thermal resistance ( ja ) ......... 37c/w junction-to-case thermal resistance ( jc ) ................ 2.8 c/w v sup , en1 to gnd ............................................... -0.3v to +45v pv_ to gnd............................ .............................. -0.3v to +6.0v pv_ to gnd................... ....................................... -0.3v to +6.0v pv2 to gnd, pv2 to pgnd2 ............................... -0.3v to +6.0v pv3 to gnd, pv3 to pgnd3 ............................... -0.3v to +6.0v pgnd2Cpgnd3 to gnd ...................................... -0.3v to +0.3v lx1 to gnd ............................................... -6.0v to v sup + 6.0v bst1 to lx1 ......................................................... -0.3v to +6.0v dh1 to lx1 ............................................... -0.3v to bst1 + 0.3v bias to gnd ........................................................ -0.3v to +6.0v dl1 to gnd ................................................. -0.3v to pv1 + 0.3v lx2 to pgnd2 ............................................. -0.3v to pv2 + 0.3v lx3 to pgnd3... .......................................... -0.3v to pv3 + 0.3v out1, cs1, out2, out3 to gnd ...................... -0.3v to +6.0v fb1, en2, en3 to gnd ........................................ -0.3v to +6.0v reset_ , err to gnd ......................................... -0.3v to +6.0v cs1 to out1 ........................................................ -0.3v to +0.3v csel1, sync, ssen to gnd ............................. -0.3v to +6.0v comp1 to gnd... .......................................... -0.3v to pv + 0.3v lx2, lx3 output short-circuit duration .................... continuous continuous power dissipation (t a = +70oc) side-wettable tqfn (derate 27mw/oc above +70oc) ............................... 2160mw operating temperature range .......................... -40oc to +125c junction temperature ...................................................... +150c storage temperature range ............................. -65oc to +150c lead temperature (soldering, 10s) ................................. +300c soldering temperature (reflow) ....................................... +260c absolute maximum ratings parameter symbol conditions min typ max units supply voltage startup threshold v sup,startup v sup rising 4.25 4.5 4.75 v supply voltage range v sup normal operation, after buck 1 startup 3.5 36 v supply current i sup v en1 = v en2 = v en3 = 0v 4 15 a v en1 = 5v, v en2 = v en3 = 0v (no load) 20 40 oscillator frequency f sw 2.0 2.1 2.2 mhz sync input frequency range 1.7 2.4 mhz spread-spectrum range v ssen = v gnd 0 % v ssen = v bias +6 bias regulator voltage v bias 6v v sup 42v, no switchover 4.6 5.0 5.4 v pv_ por v bias falling 2.5 2.7 2.9 v hysteresis 0.45 MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
maxim integrated 3 electrical characteristics (continued) (v sup = 14v, v pv1 = v bias , v pv2 = v pv3 = v out1 ; t a = t j = -40 c to +125 c, unless otherwise noted. typical values are at t a = +25 c under normal conditions, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units out1: high-voltage synchronous step-down dc-dc controller out1 switching frequency f sw1 internally generated (see the selector guide ) v csel1 = v gnd 2100 khz v csel1 = v bias (factory option) 1050 v csel1 = v bias (factory option) 525 v csel1 = v bias (factory option) 420 v csel1 = v bias (factory option) 350 voltage v out1 fixed option (see the selector guide ) v fb1 = v gnd 3.3 v v fb1 = v bias (factory option) 5.0 v fb1 = v bias (factory option) 3.15 fb1 regulation voltage adjustable option (see the selector guide ) 0.985 1.0 1.019 v error amplifer transconductance g mea 300 700 1200 s voltage accuracy v out1 5.5v v sup 18v, 0 < v lim1 < 75mv, pwm mode -2.0 +2.5 % dc load regulation pwm mode 0.02 %/a dc line regulation pwm mode 0.03 %/v out1 discharge resistance v en1 = v gnd or v sup 100 200 ? high-side output drive resistance v dh1 rising, i dh1 = 100ma 2 4 ? v dh1 falling, i dh1 = 100ma 1 4 low-side output drive resistance v dl1 rising, i dl1 = 100ma 2.5 5 ? v dl1 falling, i dl1 = 100ma 1.5 3 output current-limit threshold v lim1 csi C out1 100 120 150 mv skip current threshold i skip cs1 C out1, no load 10 35 60 mv soft-start ramp time 4 ms lx_ leakage current v lx1 = v sup 0.01 a duty-cycle range pwm mode 97.2 % minimum on-time 60 75 ns out1 ov threshold 107 110 113 % MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
maxim integrated 4 electrical characteristics (continued) (v sup = 14v, v pv1 = v bias , v pv2 = v pv3 = v out1 ; t a = t j = -40 c to +125 c, unless otherwise noted. typical values are at t a = +25 c under normal conditions, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units out2 and out3: low-voltage synchronous step-down dc-dc converters supply voltage range v sup 2.7 5.5 v supply current i pv_ v en_ = 5v, no load 0.1 5 a skip mode peak current 0.2 x i lmax ma voltage accuracy v out 0a i load i max, pwm mode -3.0 +3.0 feedback-voltage accuracy adjustable mode, i out2 = 0ma 0.806 0.815 0.824 load regulation 0a i load i max (pwm mode) -1.5 -1.0 %/a lx_ on-resistance high i lx_ = -800ma 70 110 m? lx_ on-resistance low i lx_ = 800ma 50 90 m? current-limit threshold i lmax i max = 3.0a option (see the selector guide ) 5.0 5.6 a i max = 1.5a option (see the selector guide ) 2.5 3.0 lx_ rise/fall time pv2 = pv3 = 3.3v, i out_ = 2a 4 ns soft-start ramp time 2.5 ms lx_ leakage current 0.01 a duty-cycle range pwm mode 15 100 % lx_ discharge resistance 22 48 ? reset_ reset threshold rising (relative to nominal output voltage) 92 95 98 % falling (relative to nominal output voltage) 90 92 95 out1 active timeout period see the selector guide (16,384 clocks) 7.8 ms see the selector guide (8192 clocks) 3.9 see the selector guide (4096 clocks) 1.9 see the selector guide (256 clocks) 0.1 out2, out3 active timeout period see the selector guide (16,384 clocks) 7.8 ms see the selector guide (8192 clocks) 3.9 see the selector guide (4096 clocks) 1.9 see the selector guide (256 clocks) 0.1 output low level i sink = 3ma 0.1 0.2 v propagation time out1, 5% below threshold 5 10 20 s out2/out3, 5% below threshold 2 4 8 s MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
maxim integrated 5 electrical characteristics (continued) (v sup = 14v, v pv1 = v bias , v pv2 = v pv3 = v out1 ; t a = t j = -40 c to +125 c, unless otherwise noted. typical values are at t a = +25 c under normal conditions, unless otherwise noted.) (note 2) note 2: all units are 100% production tested at t a = +25c. all temperature limits are guaranteed by design. note 3: guaranteed by design. not production tested. parameter symbol conditions min typ max units err output low level i sink = 3ma 0.1 0.2 v thermal overload thermal-warning temperature +150 c thermal-shutdown temperature +170 c thermal-shutdown hysteresis 15 c enable inputs (en_) input high v en_ rising 1.6 1.8 2.0 v hysteresis 0.2 v en input current v en_ = 5v 0.5 1.0 2.0 a synchronization i/o (sync) input high sync input option (see the selector guide ) 1.8 v input low sync input option (see the selector guide ) 0.8 v input current sync input option (see the selector guide ); v sync = 5v 50 80 a output high level sync output option (see the selector guide ); v pv = 5v, i sink = 1ma 4.9 4.98 v output low level sync output option (see the selector guide ); i sink = 1ma 0.02 0.1 v pulldown resistance 100 k? logic inputs (csel1, ssen) input high 1.4 v input low 0.5 v input current t a = +25c 2 a MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
maxim integrated 6 typical operating characteristics (v sup = 14v, t a = +25 c, unless otherwise noted) buck 2 load regulation (pwm mode) MAX16993 toc09 i out2 (a) v out2 (v) 1.4 1.2 0.8 1.0 0.4 0.6 0.2 3.09 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.08 0 1.6 t a = +125oc t a = +25oc t a = -40oc v pv2 = 5.0v, i max = 1.5a, v out2 = 3.15v buck 2 efficiency MAX16993 toc08 i out3 (a) efficiency (%) 1.00e-02 1.00e-04 10 20 30 40 50 60 70 80 90 100 0 1.00e-06 1.00e+00 s k i p m o d e p w m m o d e f sw = 2.1mhz, v sup = 14v, v pv2 = 5.0v, v out2 = 3.15v v out1 vs. temperature MAX16993 toc07 temperature (oc) v out1 (v) 100 50 0 4.985 4.990 4.995 5.000 5.005 5.010 5.015 5.020 5.025 5.030 4.980 -50 150 i out1 = 3.75a buck 1 line regulation (skip mode) MAX16993 toc06 v sup (v) v out1 (% nominal) 35 30 5 10 15 20 25 99.7 99.9 100.1 100.3 100.5 100.7 100.9 99.5 0 40 v out1 = 3.3v buck 1 line regulation (skip mode) MAX16993 toc05 v sup (v) v out1 (% nominal) 35 30 20 25 10 15 5 99.2 99.4 99.6 99.8 100.0 100.2 100.4 100.6 100.8 101.0 99.0 0 40 v out1 = 5.0v buck 1 line regulation (pwm mode) MAX16993 toc04 v sup (v) v out1 (% nominal) 35 30 20 25 10 15 5 99.6 99.7 99.8 99.9 100.0 100.1 100.2 100.3 100.4 100.5 99.5 0 40 v out1 = 5.0v t a = +125oc t a = +25oc t a = -40oc buck 1 load regulation (skip) MAX16993 toc03 i out1 (a) v out1 (v) 5 4 3 2 1 4.92 4.94 4.96 4.98 5.00 5.02 5.04 5.06 5.08 5.10 4.90 0 6 t a = +125oc t a = +25oc t a = -40oc buck 1 load regulation (pwm) MAX16993 toc02 i out1 (a) v out1 (v) 5 4 1 2 3 4.995 5.000 5.005 5.010 5.015 5.020 5.025 5.030 4.990 0 6 t a = +125oc t a = +25oc t a = -40oc buck 1 efficiency MAX16993 toc01 i out1 (a) efficiency (%) 1.00e-02 1.00e-04 10 20 30 40 50 60 70 80 90 100 0 1.00e-06 1.00e+00 s k i p m o d e p w m m o d e MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
maxim integrated 7 typical operating characteristics (continued) (v sup = 14v, t a = +25 c, unless otherwise noted) v out3 vs. temperature MAX16993 toc17 temperature (oc) v out3 (v) 100 50 0 1.785 1.790 1.795 1.800 1.805 1.810 1.780 -50 150 i out3 = 1.125a buck 3 line regulation (pwm mode) MAX16993 toc16 v pv3 (v) v out3 (% nominal) 5.3 4.8 4.3 3.8 99.6 99.7 99.8 99.9 100.0 100.1 100.2 100.3 100.4 100.5 99.5 3.3 v out3 = 1.8v t a = -40oc t a = +125oc t a = +25oc buck 3 load regulation (pwm mode) MAX16993 toc15 i out3 (a) v out3 (v) 3.0 2.5 0.5 1.0 1.5 2.0 1.216 1.218 1.220 1.222 1.224 1.226 1.228 1.230 1.214 0 3.5 v pv3 = 5.0v i max = 3a v out3 = 1.2v buck 3 load regulation (pwm mode) v out3 (v) 1.78 1.79 1.80 1.81 1.82 1.83 MAX16993 toc14 i out3 (a) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 1.77 0 1.6 t a = +125oc t a = +25oc t a = -40oc v pv3 = 5.0v, i max = 1.5a, v out3 = 1.8v buck 3 efficiency MAX16993 toc13 i out3 (a) efficiency (%) 1.00e-02 1.00e-04 10 20 30 40 50 60 70 80 90 100 0 1.00e-06 1.00e+00 s k i p m o d e p w m m o d e f sw = 2.1mhz, v sup = 14v, v pv3 = 5.0v, v out3 = 1.8v v out2 vs. temperature MAX16993 toc12 temperature (oc) v out2 (v) 100 50 0 3.105 3.110 3.115 3.120 3.125 3.130 3.135 3.140 3.145 3.150 3.100 -50 150 i out2 = 1.125a buck 2 line regulation (pwm mode) MAX16993 toc11 v pv2 (v) v out2 (% nominal) 5.2 4.7 4.2 3.7 3.2 99.2 99.4 99.6 99.8 100.0 100.2 100.4 100.6 100.8 101.0 99.0 2.7 5.7 v out2 = 3.15v t a = -40oc t a = +125oc t a = +25oc buck 2 load regulation (pwm mode) MAX16993 toc10 i out2 (a) v out2 (v) 3.0 2.5 2.0 1.5 1.0 0.5 3.315 3.320 3.325 3.330 3.335 3.340 3.345 3.310 0 3.5 v pv2 = 5.0v i max = 3a v out2 = 3.3v MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
maxim integrated 8 typical operating characteristics (continued) (v sup = 14v, t a = +25 c, unless otherwise noted) spectral energy density MAX16993 toc24 frequency (mhz) output spectrum (dbv) 2.25 2.20 2.15 2.10 2.05 2.00 1.95 0 10 20 30 40 50 60 -10 1.90 2.30 ss disabled ss enabled shutdown current vs. supply voltage MAX16993 toc23 v sup (v) shutdown current (a) 35 30 20 25 10 15 5 1 2 3 4 5 6 7 8 9 10 0 0 40 t a = +125oc t a = +25oc t a = -40oc v en1 = v en2 = v en3 = v gnd measured at v sup f sw vs. temperature MAX16993 toc22 temperature (oc) switching frequency (% nominal) 100 50 0 98 99 100 101 102 103 97 -50 150 f sw = 2.1mhz load transient response (pwm mode) MAX16993 toc21 200s/div v out1 i out1 100mv/div 1a/div supply current vs. supply voltage MAX16993 toc20 v sup (v) supply current (a) 35 30 25 20 15 10 5 10 20 30 40 50 60 70 0 0 40 t a = +125oc t a = +25oc t a = -40oc v out1 = 5.0v, skip mode only buck controller enabled supply current vs. supply voltage MAX16993 toc19 v sup (v) supply current (a) 35 30 25 20 15 10 5 20 40 60 80 100 120 0 0 40 t a = +125oc t a = +25oc t a = -40oc v fb = v gnd skip mode all three bucks enabled measured at v sup startup sequence (v en2 = v en3 = v out1 ) MAX16993 toc18 2ms/div v en1 v out1 v reset1 v out2 v reset2 v out3 v reset3 5v/div 5v/div 5v/div 5v/div 5v/div 5v/div 5v/div MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
maxim integrated 9 pin description pin confguration pin name function 1 pv1 supply input for buck 1 low-side gate drive. connect a ceramic bypass capacitor of at least 0.1f from pv1 to gnd. 2 dl1 low-side gate-drive output for buck 1. dl1 output voltage swings from v gnd to v pv1 . 3 gnd power ground for buck 1 4 lx1 inductor connection for buck 1. connect lx1 to the switched side of the inductor. lx1 serves as the lower supply rail for the dh1 high-side gate drive. 5 dh1 high-side gate-drive output for buck 1. dh1 output voltage swings from v lx1 to v bst1 . 6 bst1 bootstrap capacitor connection for high-side gate drive of buck 1. connect a high-voltage diode between bias and bst1. connect a ceramic capacitor between bst1 and lx1. see the high-side gate-drive supply (bst1) section. 7 v sup supply input. bypass v sup with a minimum 0.1f capacitor as close as possible to the device. 8 en1 high-voltage tolerant, active-high digital enable input for buck 1. driving en1 high enables buck 1. 9 bias 5v internal linear regulator output. bypass bias to gnd with a low-esr ceramic capacitor of 2.2f minimum value. bias provides the power to the internal circuitry. see the linear regulator (bias) section. 10 pv analog supply. connect pv to bias through a 10? resistor and connect a 0.1f ceramic capacitor from pv to ground. 11 fb1 feedback input for buck 1. for the fxed output-voltage option, connect fb1 to bias for the factory-trimmed (3.0v to 3.75v or 4.6v to 5.35v) fxed output. connect fb1 to gnd for the 3.3v fxed output. for the resistor- divider adjustable output-voltage option, connect fb1 to a resistive divider between out1 and gnd to adjust the output voltage between 3.0v and 5.5v. in adjustable mode, fb1 regulates to 1.0v (typ). see the out1 adjustable output-voltage option section. MAX16993 side-wettable tqfn top view 29 30 28 27 12 11 13 dl1 lx1 dh1 bst1 v sup 14 pv1 pv2 pgnd2 pgnd3 reset 2 lx3 pv3 12 reset1 45 67 23 24 22 20 19 18 gnd comp1 ep = gnd en2 out1 cs1 fb1 gnd lx2 3 21 31 10 err pv 32 9 sync bias + ssen 26 15 en3 csel1 25 16 out3 en1 reset 3 8 17 out2 MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
maxim integrated 10 pin description (continued) pin name function 12 cs1 positive current-sense input for buck 1. connect cs1 to the positive terminal of the current-sense resistor. see the current-limit/short-circuit protection and current-sense measurement sections. 13 out1 output sense and negative current-sense input for buck 1. the buck uses out1 to sense the output voltage. connect out1 to the negative terminal of the current-sense resistor. see the current-limit/short-circuit protection and current-sense measurement sections. 14 en2 active-high digital enable input for buck 2. driving en2 high enables buck 2. 15 en3 active-high digital enable input for buck 3. driving en3 high enables buck 3. 16 out3 buck converter 3 voltage-sense input. connect out3 to the output of buck 3. connect out3 to an external feedback divider when setting dc-dc3 voltage externally. see the out2/out3 adjustable output-voltage option section. 17 reset3 open-drain buck 3 reset output. reset3 remains low for a fxed time after the output of buck 3 has reached its regulation level (see the selector guide ). to obtain a logic signal, pull up reset3 with an external resistor connected to a positive voltage lower than 5v. 18 pv3 buck 3 voltage input. connect a 2.2f or larger ceramic capacitor from pv3 to pgnd3. connect pv3 to out1. 19 lx3 buck 3 switching node. lx3 is high impedance when the device is off. 20 pgnd3 power ground for buck 3 21 pgnd2 power ground for buck 2 22 lx2 buck 2 switching node. lx2 is high impedance when the device is off. 23 pv2 buck 2 voltage input. connect a 2.2f or larger ceramic capacitor from pv2 to pgnd2. connect pv2 to out1. 24 reset2 open-drain buck 2 reset output. this output remains low for a fxed time after the output of buck 2 has reached its regulation level (see the selector guide ). to obtain a logic signal, pull up reset2 with an external resistor connected to a positive voltage lower than 5v. 25 out2 buck converter 2 voltage-sense input. connect out2 to the output of buck 2. connect out2 to an external feedback divider when setting dc-dc2 voltage externally. see the out2/out3 adjustable output-voltage option section. 26 csel1 buck 1 clock select. connect csel1 to gnd for 2.1mhz operation. connect csel1 to bias for an otp- programmable divide-down operation. see the selector guide for the f sw1 divide ratio. 27 ssen spread-spectrum enable. connect ssen to gnd for standard oscillator operation. connect ssen to bias to enable the spread-spectrum oscillator. 28 reset1 open-drain buck 1 reset output. reset1 remains low for a fxed time after the output of buck 1 has reached its regulation level (see the selector guide ). to obtain a logic signal, pull up reset1 with an external resistor connected to a positive voltage lower than 5v. 29 gnd analog ground 30 comp1 compensation for buck 1. see the compensation network section. 31 err open-drain error-status output. err signals a thermal-warning/shutdown condition. to obtain a logic signal, pull up err with an external resistor connected to a positive voltage lower than 5v. 32 sync synchronization input. sync allows the device to synchronize to other supplies. connect sync to gnd or leave unconnected to enable skip-mode operation under light loads. connect sync to bias or an external clock to enable fxed-frequency forced-pwm-mode operation. ep exposed pad. connect the exposed pad to ground. connecting the exposed pad to ground does not remove the requirement for proper ground connections to pgnd2Cpgnd3 and gnd. the exposed pad is attached with epoxy to the substrate of the die, making it an excellent path to remove heat from the ic. MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
maxim integrated 11 typical operating circuit v out1 v ba tp n n p p linear regula to r MAX16993 step-down controller out1 step-down pwm out3 0.8v to 3.95v 1.5a to 3.0a bias dh1 pv pv1 bias pv3 lx3 v out3 v out1 pgnd3 out3 pv2 lx2 v out2 v out1 pgnd2 out2 lx1 gnd cs1 out1 fb1 pwm en pwm en pwm ep en por genera tion and control comp1 reset1 dl1 n n gnd bst1 v sup reset2 reset3 en1 en2 en3 err ssen csel1 sync step-down pwm out2 0.8v to 3.95v 1.5a to 3.0a MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
maxim integrated 12 detailed description the MAX16993 power-management integrated circuit (pmic) is a 2.1mhz, multichannel, dc-dc converter designed for automotive applications. the device includes one high-voltage step-down controller (out1) designed to run directly from a car battery and two low-voltage step- down converters (out2/out3) cascaded from out1. the 2.1mhz, high-voltage buck controller operates with a 3.5v to 36v input voltage range and is protected from load-dump transients up to 42v. the high-frequency operation eliminates am band interference and reduces the solution footprint. it can provide an output voltage between 3.0v and 5.5v set at the factory or with external resistors. each device has two frequency options that are pin selectable: 2.1mhz or a lower frequency based on factory setting. available factory-set frequencies are 1.05mhz, 525khz, 420khz, or 350khz. under no-load conditions, the device consumes only 30a of quiescent current with out1 enabled. the dual buck converters can deliver 1.5a or 3.0a of load current per output. they operate directly from out1 and provide 0.8v to 3.95v output voltage range. factory trimmed output voltages achieve 3% output error over load, line, and temperature without using expensive 0.1% resistors. in addition, adjustable output-voltage versions can be set to any desired values between 0.8v and 3.6v using an external resistive divider. on-board low r ds(on) switches help minimize efficiency losses at heavy loads and reduce critical/parasitic inductance, mak - ing the layout a much simpler task with respect to discrete solutions. following a simple layout and footprint ensures first-pass success in new designs (see the pcb layout guidelines section). the device features either a sync input or sync output (see the synchronization (sync) section and the selector guide ). an optional spread-spectrum frequency modula - tion minimizes radiated electromagnetic emissions due to the switching frequency, and a factory-programmable synchronization i/o (sync) allows better noise immunity. additional features include a 4ms fixed soft-start for out1 and 2.5ms for out2/out3, individual reset_ outputs, overcurrent, and overtemperature protections. see the selector guide for the available options. enable inputs (en_) all three regulators have their own enable input. when en1 exceeds the en1 high threshold, the internal lin - ear regulator is switched on. when v sup exceeds the v sup,startup threshold, buck 1 is enabled and out1 starts to ramp up with a 3ms soft-start. once the buck 1 soft-start is complete, buck 2 and buck 3 can be enabled. when either buck 2 or buck 3 is enabled, the correspond - ing output ramps up with a 2.5ms soft-start. when an enable input is pulled low, the converter is switched off and the corresponding out_ and reset_ are driven low. if en1 is low, all regulators are disabled. reset outputs ( reset_ ) the device features individual open-drain reset_ out - puts for each buck output that asserts when the buck output voltage drops 6% below the regulated voltage. reset_ remains asserted for a fixed timeout period after the buck output rises up to its regulated voltage. the fixed timeout period is programmable between 0.1ms and 7.4ms (see the selector guide ). to obtain a logic signal, pull up reset_ with an external resistor connected to a positive voltage lower than 5v. linear regulator (bias) the device features a 5v internal linear regulator (bias). connect bias to pv, which acts as a supply for internal circuitry. also connect bias to pv1, which acts as a supply for the low-side gate driver of buck 1. bypass bias with a 2.2f or larger ceramic capacitor as close as possible to the device. bias can provide up to 100ma (max), but is not designed to supply external loads. internal oscillator buck 1 clock select (csel1) the device offers a buck 1 clock-select input. connect csel1 to gnd for 2.1mhz operation. connect csel1 to bias to divide down the buck 1 clock frequency by 2, 4, 5, or 6 (see the selector guide ). buck 2 and buck 3 switch at 2.1mhz (typ) and are not controlled by csel1. MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
maxim integrated 13 spread-spectrum enable (ssen) the device features a spread-spectrum enable (ssen) input that can quickly enable spread-spectrum operation to reduce radiated emissions. connect ssen to bias to enable the spread-spectrum oscillator. connect ssen to gnd for standard oscillator operation. when spread spectrum is enabled, the internal oscillator frequency is varied between f sw and (f sw + 6%). the change in frequency has a sawtooth shape and a frequency of 4khz (see figure 1 ). this function does not apply to externally applied oscillation frequency. see the selector guide for available options. synchronization (sync) sync is factory-programmable i/o. see the selector guide for available options. when sync is configured as an input, a logic-high on sync enables fixed-frequency, forced-pwm mode. apply an external clock on the sync input to synchronize the internal oscillator to an external clock. the sync input accepts signal frequencies in the range of 1.7mhz < f sync < 2.4mhz. the external clock should have a duty cycle of 50%. a logic-low at the sync input enables the device to enter a low-power skip mode under light-load conditions. when sync is configured as an output, sync outputs the internally generated 2.1mhz clock that switches from v pv to v gnd . all converters operate in forced-pwm mode when sync is configured as an output. common protection features undervoltage lockout the device offers an undervoltage-lockout feature. undervoltage detection is performed on the pv input. if v sup decreases to the point where buck 1 is in drop - out, pv begins to decrease. if pv falls below the uvlo threshold (2.7v, typ), all three converters switch off and the reset_ outputs assert low. once the device has been switched off, v sup must exceed the v sup,startup threshold before buck 1 turns back on. output overvoltage protection the device features overvoltage protection on the buck converter outputs. if the fb1 input exceeds the output overvoltage threshold, a discharge current is switched on at out1 and reset1 asserts low. figure 1. effect of spread spectrum on internal oscillator f sw + 6% f sw tt + 250s t + 500s t + 750s internal oscilla to r frequency time MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
maxim integrated 14 soft-start the device includes a 4ms fixed soft-start time on out1 and 2.5ms fixed soft-start time on out2/out3. soft-start time limits startup inrush current by forcing the output voltage to ramp up towards its regulation point. if out1 is prebiased above 1.25v, all three buck converters do not start up until the prebias has been removed. once the prebias has been removed, out1 self-discharges to gnd and then goes into soft-start. thermal warning and overtemperature protection the device features an open-drain, thermal-warning indicator ( err ). err asserts low when the junction temperature exceeds +145c (typ). for a logic signal, connect a pullup resistor from err to a supply less than or equal to 5v. when the junction temperature exceeds +170c (typ), an internal thermal sensor shuts down the buck converters, allowing the device to cool. the thermal sensor turns the device on again after the junction temperature cools by 30c (typ). buck 1 (out1) buck controller 1 uses a pwm current-mode control scheme. an internal transconductance amplifier estab - lishes an integrated error voltage. the heart of the pwm controller is an open-loop comparator that compares the integrated voltage-feedback signal against the amplified current-sense signal plus the slope-compensation ramp, which are summed into the main pwm comparator to preserve inner-loop stability and eliminate inductor stair - casing. at each rising edge of the internal clock, the high- side mosfet turns on until the pwm comparator trips or the maximum duty cycle is reached, or the peak current limit is reached. during this on-time, current ramps up through the inductor, storing energy in a magnetic field and sourcing current to the output. the current-mode feedback system regulates the peak inductor current as a function of the output-voltage error signal. the circuit acts as a switch-mode transconductance amplifier and pushes the output lc filter pole normally found in a voltage-mode pwm to a higher frequency. during the second half of the cycle, the high-side mosfet turns off and the low-side mosfet turns on. the inductor releases the stored energy as the current ramps down, providing current to the output. the out - put capacitor stores charge when the inductor current exceeds the required load current and discharges when the inductor current is lower, smoothing the voltage across the load. under soft-overload conditions, when the peak inductor current exceeds the selected current limit (see the current-limi t / short-circuit protection section), the high-side mosfet is turned off immediately and the low-side mosfet is turned on and remains on to let the inductor current ramp down until the next clock cycle. pwm/skip modes the device features a synchronization input that puts all the buck regulators either in skip mode or forced-pwm mode of operation (see the synchronization (sync) section). in the pwm mode of operation, the regulator switches at a constant frequency with variable on-time. in the skip mode of operation, the regulators switching frequency is load dependent until the output load reaches a certain threshold. at higher load current, the switch - ing frequency does not change and the operating mode is similar to the pwm mode. skip mode helps improve efficiency in light-load applications by allowing the regula - tor to turn on the high-side switch only when the output voltage falls below a set threshold. as such, the regulator does not switch mosfets on and off as often as is the case in the pwm mode. consequently, the gate charge and switching losses are much lower in skip mode. minimum on-time and duty cycle the high-side gate driver for buck 1 has a minimum on- time of 75ns (max). this helps ensure no skipped pulses when operating the device in pwm mode at 2.1mhz with supply voltage up to 18v and output voltage down to 3.3v. pulse skipping can occur if the on-time falls below the minimum allowed (see the electrical characteristics ). current-limit /short-circuit protection out1 offers a current-limit feature that protects buck 1 against short-circuit and overload conditions on the buck controller. buck 1 offers a current-limit sense input (cs1). place a sense resistor in the path of the channel 1 current flow. connect cs1 to the high side of the sense resistor and out1 to the low side of the sense resistor. current- limit protection activates once the voltage across the sense resistor increases above the 120mv (typ) current- limit threshold. in the event of a short-circuit or overload condition, the high-side mosfet remains on until the inductor current reaches the current-limit threshold. the converter then turns on the low-side mosfet and the inductor current ramps down. the converter allows the high-side mosfet to turn on only when the voltage across the current-sense resistor ramps down to below 120mv (typ). this cycle repeats until the short or overload condition is removed. MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
maxim integrated 15 current-sense measurement for the best current-sense accuracy and overcurrent pro - tection, use a 1% tolerance current-sense resistor between the inductor and output, as shown in figure 2a . this con - figuration constantly monitors the inductor current, allow - ing accurate current-limit protection. use low-inductance current-sense resistors for accurate measurement. lossless inductor dcr sensing high-power applications that do not require highly accu - rate current-limit protection can reduce the overall power dissipation by connecting a series rc circuit across the inductor (see figure 2b ) with an equivalent time constant: 2 cseq dcr 12 dcr eq 1 2 r rr rr and: l 11 r c rr ?? = ?? ?? + ?? ?? = + ?? ?? ?? where r cseq is the required current-sense resistor and r dcr is the inductors series dc resistance. use the inductance and r dcr values provided by the inductor manufacturer. carefully observe the pcb layout guidelines to ensure the noise and dc errors do not corrupt the differential current- sense signals seen by cs1 and out1. place the sense resistor close to the device with short, direct traces, making a kelvin-sense connection to the current-sense resistor. high-side gate-drive supply (bst1) the high-side mosfet is turned on by closing an inter - nal switch between bst1 and dh1 and transferring the bootstrap capacitors (at bst1) charge to the gate of the high-side mosfet. this charge refreshes when the high- side mosfet turns off and the lx1 voltage drops down to ground potential, taking the negative terminal of the capacitor to the same potential. at this time, the bootstrap diode recharges the positive terminal of the bootstrap capacitor. the selected n-channel high-side mosfet determines the appropriate boost capacitance values (c bst1 in the typical operating circuit ) according to the following equation: g bst 1 bst 1 q c v = ? where q g is the total gate charge of the high-side mosfet and v bst1 is the voltage variation allowed on the high-side mosfet driver after turn-on. choose v bst1 such that the available gate-drive voltage is not significantly degraded (e.g., v bst1 = 100mv to 300mv) when determining c bst1 . use a schottky diode when efficiency is most important, as this maximizes the gate- drive voltage. if the quiescent current at high temperature is important, it may be necessary to use a low-leakage switching diode. the boost capacitor should be a low-esr ceramic capaci - tor. a minimum value of 100nf works in most cases. a minimum value of 470nf is recommended when using a schottky diode. figure 2. current-sense configurations dh1 a) output series resisit or sensing r cseq = r dcr r1 r1 + r2 lx1 gnd cs1 out1 dl1 n n l1 r cs v sup c in c out MAX16993 dh1 b) lossless induct or dcr sensing lx1 gnd cs1 out1 dl1 n n l1 r dcr r1 r2 c eq v sup induct or c in c out MAX16993 r dcr = + 1 r1 1 r2 l c eq MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
maxim integrated 16 dropout when out1 input voltage is lower than the desired output voltage, the converter is in dropout mode. buck 1 continu - ously draws current from the bootstrap capacitor when the high-side switch is on. therefore, the bootstrap capacitor needs to be refreshed periodically. when in dropout, the buck 1 high-side gate drive shuts off every 8s, at which point the low-side gate drive turns on for 120ns. buck 2 and buck 3 (out2 and out3) buck converters 2 and 3 are high-efficiency, low-voltage converters with integrated fets. they use a pwm current-mode control scheme that is operated at 2.1mhz to optimize component size and efficiency, while elimi - nating am band intererence. the buck converters can be configured to deliver 1.5a or 3.0a per channel. they operate directly from out1 and have either fixed or resistor-programmable (see the selector guide ) output voltages that range from 0.8v to 3.95v. buck 2 and buck 3 feature low on-resistance internal fets that contribute to high efficiency and smaller system cost and board space. integration of the p-channel high-side fet enables both channels to operate with 100% duty cycle when the input voltage falls to near the output voltage. they feature a programmable active timeout period (see the selector guide ) that adds a fixed delay before the corresponding reset_ can go high. fpwm/skip modes the MAX16993 features an input (sync) that puts the converter either in skip mode or forced pwm (fpwm) mode of operation. see the internal oscillator section. in fpwm mode, the converter switches at a constant frequency with variable on-time. in skip mode, the con - verters switching frequency is load-dependent until the output load reaches a certain threshold. at higher load current, the switching frequency does not change and the operating mode is similar to the fpwm mode. skip mode helps improve efficiency in light-load appli - cations by allowing the converters to turn on the high- side switch only when the output voltage falls below a set threshold. as such, the converter does not switch mosfets on and off as often as is the case in the fpwm mode. consequently, the gate charge and switching losses are much lower in skip mode. current-limit/short-circuit protection buck converters 2 and 3 feature current limit that protects the device against short-circuit and overload conditions at their outputs. the current limit value is dependent on the version selected, 1.5a or 3.0a maximum dc current. see the selector guide for the current limit value of the chosen option and the electrical characteristics table for the cor - responding current limit. in the event of a short-circuit or overload condition at an output, the high-side mosfet remains on until the inductor current reaches the high- side mosfets current-limit threshold. the converter then turns on the low-side mosfet and the inductor cur - rent ramps down. the converter allows the high-side mosfet to turn off only when the inductor current ramps down to the low- side mosfets current threshold. this cycle repeats until the short or overload condition is removed. applications information out1 adjustable output-voltage option the devices adjustable output-voltage version (see the selector guide for details) allows the customer to set out1 voltage between 3.0v and 5.5v. connect a resis - tive divider from out1 to fb1 to gnd to set the output voltage ( figure 3 ). select r2 (fb1 to gnd resistor) less than or equal to 100k?. calculate r1 (v out1 to fb1 resistor) with the following equation: out 1 12 fb 1 v rr 1 v ?? ?? = ? ?? ?? ?? ?? ?? ?? where v fb1 = 1.0v (see the electrical characteristics ). the external feedback resistive divider must be frequency compensated for proper operation. place a capacitor across r1 in the resistive divider network. use the follow - ing equation to determine the value of the capacitor: if r2/r1 > 1, c1 = c(r2/r1) else, c1 = c, where c = 10pf. for fixed output options, connect fb1 to bias for the factory-programmed, fixed output voltage. connect fb1 to gnd for a fixed 3.3v output voltage. figure 3. adjustable out1 voltage configuration r1 v out1 c1 out1 MAX16993 fb1 r2 MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
maxim integrated 17 table 1. inductor values vs. (v supmax, v out1 ) out1 current-sense resistor selection choose the current-sense resistor based on the maximum inductor current ripple (k indmax ) and minimum current-limit threshold across current-sense resistor (v lim1min = 0.1v). the formula for calculating the current-sense resistor is: lim1min max indmax outmax v rcs k i (1 ) 2 = + where i outmax is the maximum load current for buck 1 and k indmax is the maximum inductor current ripple. the maximum inductor current ripple is a function of the inductor chosen, as well as the operating conditions, and is typically chosen between 0.3 and 0.4: [ ] [ ] sup out indmax outmax sw 1 (v v ) d k i f mhz l h ? = where d is the duty cycle. below is a numerical example to calculate the current-sense resistor in figure 2a . the maximum inductor current ripple is chosen at the maximum supply voltage (36v) to be 0.4: max indmax outmax 0.1 rcs k i1 2 0.1 0.0166 0.4 51 2 = ?? + ?? ?? = = ? ?? + ?? ?? out1 inductor selection three key inductor parameters must be specified for operation with the device: inductance value (l), inductor saturation current (i sat ), and dc resistance (r dcr ). use the following formulas to determine the minimum inductor value: ( ) out 1 supmax out 1 supmax min 1 sw 1 outmax indmax v vv v l [ h ] 1.3 1 fi k ?? ?? ? ?? ?? ?? ?? ?? = ?? ?? ?? ?? ?? ?? ?? ?? where f sw1 is the operating frequency and 1.3 is a coefficient that accounts for inductance initial precision. or out1 min 2 cs 6 v_cs sw1 v l [ h ] 1.3 r 0.8 2.1 10 a f = where a v_cs is current-sense amplifier gain (8v/v, typ). for proper operation, the chosen inductor value must be greater than or equal to l min1 and l min2 . the maximum inductor value recommended is twice the chosen value from the above formulas. table 1 lists some of the inductor values for 5a output current and several switching frequencies and output voltages. buck 1 input capacitor the device is designed to operate with a single 0.1f capacitor on the v sup input and a single 0.1f capacitor on the pv1 input. place these capacitors as close as pos - sible to their corresponding inputs to ensure the best emi and jitter performance. v supmax to v out1 (v) v supmax = 36v, v out1 = 5v v supmax = 36v, v out1 = 3.3v f sw1 (mhz) 2.1 1.05 0.525 0.420 0.350 2.1 1.05 0.525 0.420 0.350 inductor (h), i load = 5a 1.5 3.3 5.6 6.8 8.2 1.0 2.2 4.7 4.7 6.8 MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
maxim integrated 18 out1 output capacitor the primary purpose of the out1 output capacitor is to reduce the change in v out1 during load transient condi - tions. the minimum capacitor depends on the output volt - age, maximum current, and load regulation accuracy. use the following formula to determine the minimum output capacitor for buck 1: out1(max) out out1 co out1 out1 i c v 2f v v ? where f co is the crossover frequency set by r c and c c , and v out1 is the allowable change in voltage during a load transient condition. for proper functionality, ceramic capacitors must be used. make sure that the self-resonance of the ceramic capaci - tors is above 1mhz to avoid instability. buck 1 mosfet selection buck 1 drives two external logic-level n-channel mosfets as the circuit switch elements. the key selection param - eters to choose these mosfets are: on-resistance (r ds(on) ) maximum drain-to-source voltage (v ds(max) ) minimum threshold voltage (v th(min) ) total gate charge (q g ) reverse transfer capacitance (c rss ) power dissipation both n-channel mosfets must be logic-level types with guaranteed on-resistance specifications at v gs = 4.5v when v out1 is set to 5v or v gs = 3v when v out1 is set to 3.3v. the conduction losses at minimum input voltage should not exceed mosfet package thermal limits or violate the overall thermal budget. also, ensure that the conduction losses plus switching losses at the maximum input voltage do not exceed package ratings or violate the overall thermal budget. in particular, check that the dv/dt caused by dh1 turning on does not pull up the dl1 gate through its drain-to-gate capacitance. this is the most frequent cause of cross-conduction problems. gate-charge losses are dissipated by the driver and do not heat the mosfet. therefore, the power dissipation in the device due to drive losses must be checked. both mosfets must be selected so that their total gate charge is low enough; therefore, pv1/ v out1 can power both drivers without overheating the device: p drive = v out1 x (q gtoth + q gtotl ) x f sw1 where q gtotl is the low-side mosfet total gate charge and q gtoth is the high-side mosfet total gate charge. select mosfets with a q g_ total of less than 10nc. the n-channel mosfets must deliver the average current to the load and the peak current during switching. dual mosfets in a single package can be an economical solution. to reduce switching noise for smaller mosfets, use a series resistor in the dh1 path and additional gate capacitance. contact the factory for guidance using gate resistors. compensation network the device uses a curren t-mode-control scheme that regulates the output voltage by forcing the required current through the external inductor, so the controller uses the voltage drop across the dc resistance of the inductor or the alternate series current-sense resistor to measure the inductor current. current-mode control eliminates the double pole in the feedback loop caused by the inductor and output capacitor, resulting in a smaller phase shift and requiring less elaborate error-amplifier compensation than voltage-mode control. a single series resistor (r c ) and capacitor (c c ) is all that is required to have a stable, high-bandwidth loop in applications where ceramic capacitors are used for output filtering (see figure 4 ). for other types of capacitors, due to the higher capacitance and esr, the frequency of the zero created by the capacitance and esr is lower than the desired closed-loop crossover frequency. to stabilize a nonceramic output capacitor loop, add another compen - sation capacitor (c f ) from comp1 to gnd to cancel this esr zero. figure 4. compensation network r1 r esr r c c f c c 30m comp_ c out r2 cs_ out_ fb_ v ref current-mod e power modulation g mc = 1/( a vcs x r dc ) erro r am p g mea = 660s MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
maxim integrated 19 the basic regulator loop is modeled as a power modu - lator, output feedback divider, and an error amplifier (see figure 4 ). the power modulator has a dc gain set by g mc x r load , with a pole and zero pair set by r load , the output capacitor (c out ), and its esr. the loop response is set by the following eq uation: gain mod(dc) = g mc x r load where r load = v out /i lout(max) in ? and g mc = 1/ (a v_cs x r dc ) in s. a v_cs is the voltage gain of the cur - rent-sense amplifier and is typically 8v/v. r dc is the dc resistance of the inductor or the current-sense resistor in ?. in a current-mode step-down converter, the output capaci - tor and the load resistance introduce a pole at the follow - ing frequency: pmod out load 1 f 2c r = the unity-gain frequency of the power stage is set by c out and g mc : mc ugainpmod out g f 2c = the output capacitor and its esr also introduce a zero at: zmod out 1 f 2 esr c = when c out is composed of n identical capacitors in parallel, the resulting c out = n x c out(each) , and esr = esr (each) /n. note that the capacitor zero for a parallel combination of like-value capacitors is the same as for an individual capacitor. the feedback voltage-divider has a gain of gain fb = v fb /v out , where v fb is 1v (typ). the transconductance error amplifier has a dc gain of gain ea(dc) = g m,ea x r out,ea , where g m,ea is the error amplifier transconductance, which is 660s (typ), and r out,ea is the output resistance of the error ampli - fier, which is 30m? (typ). a dominant pole (f dpea ) is set by the compensation capac - itor (c c ) and the amplifier output resistance (r out,ea ). a zero (f zea ) is set by the compensation resistor (r c ) and the compensation capacitor (c c ). there is an optional pole (f pea ) set by c f and r c to cancel the output capaci - tor esr zero if it occurs near the crossover frequency (f c , where the loop gain equals 1 (0db)). thus: dpea c out,ea c zea cc pea fc 1 f 2 c (r r ) 1 f 2c r 1 f 2c r = + = = the loop-gain crossover frequency (f c ) should be set below 1/5 of the switching frequency and much higher than the power-modulator pole (f pmod ). select a value for f c in the range: sw pmod c f ff 5 << at the crossover frequency, the total loop gain must be equal to 1. thus: cc c c fb mod ( f ) ea ( r ) out ea (f ) m,ea c pmod mod ( f ) mod ( dc ) c v gain gain 1 v gain g f f gain gain f = = = therefore: c fb mod (f ) m,ea c out v gain g r 1 v = solving for r c : c out c m,ea fb mod (f ) v r g v gain = set the error-amplifier compensation zero formed by r c and c c at the f pmod . calculate the value of c c as follows: c c 1 c 2f r pmod = if f zmod is less than 5 x f c , add a second capacitor c f from comp1 to gnd. the value of c f is: f c 1 c 2f r zmod = MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
maxim integrated 20 as the load current decreases, the modulator pole also decreases; however, the modulator gain increases accord - ingly and the crossover frequency remains the same. below is a numerical example to calculate the compensa - tion network component values of figure 4 : a v_cs = 8v/v r dcr = 22m? g mc = 1/(a v_cs x r dc ) = 1/(8 x 0.022) = 5.68 v out = 5v i out(max) = 5a r load = v out/iout(max) = 5v/6a = 0.833? c out = 4 x 47f = 188f esr = 9m?/4 = 2.25m? f sw = 0.420mhz gain mod(dc) = 5.68 x 0.833 = 4.73 pmod sw pmod c cc zmod 1 f 1khz 2 188 f 0.833 f ff 5 1khz f 80.6 khz , select f 20 khz 1 f 376 khz 2 2.25 m 188 f = << << = = ? since f zmod > f c : r c 33k? c c 4.7nf c f 12pf out2/out3 adjustable output-voltage option the devices adjustable output-voltage version (see the selector guide for details) allows the customer to set the outputs to any voltage between 0.8v and 3.95v. connect a resistive divider from the buck converter output (v out_(buck) ) to out_ to gnd to set the output voltage ( figure 5 ). select r4 (out_ to gnd resistor) less than or equal to 100k?. calculate r3 (v out_(buck) ) to out_ resistor) with the following equation: out_( buck ) out_ v r3 r4 1 v ?? ?? ?? ?? = ? ?? ?? ?? ?? where v out_ = 812mv (see the electrical characteristics ). the external feedback resistive divider must be frequency compensated for proper operation. place a capacitor across r1 in the resistive divider network. use the follow - ing equation to determine the value of the capacitor: if r4/r3 > 1, c2 = c(r4/r3) else, c2 = c, where c = 10pf. for fixed output-voltage options, connect out_ to v out_ for the factory-programmed, fixed-output voltage between 0.8v and 3.95v. out2/out3 inductor selection three key inductor parameters must be specified for operation with the device: inductance value (l), inductor saturation current (i sat ), and dc resistance (r dcr ). use the following formulas to determine the minimum inductor value: ( ) out_ min1 in out_ in op ref cs v 3 l vv v fv g =? ?? v ref reference voltage, v ref = 1.25v. g cs internal current sense conductance. see the selector guide for the value for each specifc part number. g cs = 0.8s; for 1.5a output channels g cs = 1.6s; for 3.0a output channels f op operating frequency. this value is 2.1mhz, unless externally synchronized to a different frequency. figure 5. adjustable out2/out3 voltage configuration r3 v out_(buck) c2 MAX16993 out_ lx_ r4 MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
maxim integrated 21 table 3. output capacitor values vs. v out table 2. inductor values vs. (v pv_, v out ) the next equation ensures that the inductor current down slope is less than the internal slope compensation. for this to be the case, the following equation needs to be satisfied: m2 m 2 ? -m slope compensation, [0.8 x v ref /(s x g cs )] m2 inductor current downslope, [v out /l] solving for l: min2 out ref cs s lv 1.6 v g = ?? the equation that provides the bigger inductor value must be chosed for proper operation. l min = max(l min1 , l min2 ) the maximum inductor value recommended is twice the chosen value from the above formula. l max = 2 x l min out2/out3 input capacitor place a single 4.7f ceramic bypass capacitor on the pv2 and pv3 inputs. phase interleaving of the two low- voltage buck converters contributes to a lower required input capacitance by cancelling input ripple currents. place the bypass capacitors as close as possible to their corresponding pv_ input to ensure the best emi and jitter performance. out2 /out3 output capacitor the minimum capacitor required depends on output volt - age, maximum device current capability, and the error amplifier voltage gain. use the following formula to deter - mine the required output capacitor value: ref cs eamp out(min) co out v gg c 2f v ?? = ? ? v ref reference voltage, v ref = 1.25v. g cs internal current sense conductance. see the selector guide for the value for each specifc part number. g cs = 0.8s; for 1.5a output channels g cs = 1.6s; for 3.0a output channels f co target crossover frequency, 250khz. g eamp error amplifer voltage gain is 50v/v g eamp = 50v/v where v ref is the crossover frequency. table 3 lists some of the capacitor values for 1.5a output current and several output voltages. for prop - er functionality, ceramic capacitors must be used. make sure that the self-resonance of the ceramic capacitors at the converters output converter is above 1mhz to avoid instability. v out (v) 3.3 2.5 1.5 0.8 c out (f), i max = 1.5a 12 15 25 48 v pv_ to v out (v) v pv2/3 = 5.5v, v out2/3 = 3.3v v pv2/3 = 5.5v, v out2/3 = 2.5v v pv2/3 = 5.5v, v out2/3 = 1.5v v pv2/3 = 3.0v, v out2/3 = 0.8v inductor (h), i load = 1.5a 2.2 1.5 1.0 0.56 inductor (h), i load = 3.0a 1.0 0.68 0.56 0.33 MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
maxim integrated 22 thermal considerations how much power the package can dissipate strongly depends on the mounting method of the ic to the pcb and the copper area for cooling. using the jedec test standard, the maximum power dissipation allowed is 2160mw in the side-wettable tqfn package. more power dissipation can be handled by the package if great attention is given during pcb layout. for example, using the top and bottom copper as a heatsink and connect - ing the thermal vias to one of the middle layers (gnd) transfers the heat from the package into the board more efficiently, resulting in lower junction temperature at high power dissipation in some MAX16993 applications. furthermore, the solder mask around the ic area on both top and bottom layers can be removed to radiate the heat directly into the air. the maximum allowable power dis - sipation in the ic is as follows: j ( max ) a max jc ca (t t ) p ? = + where t j(max) is the maximum junction temperature (+150c), t a is the ambient air temperature, jc (2.8c/w for the side-wettable tqfn) is the thermal resistance from the junction to the case, and ca is the thermal resistance from the case to the surrounding air through the pcb, copper traces, and the package materials. ca is directly related to system-level variables and can be modified to increase the maximum power dissipation. the tqfn package has an exposed thermal pad on its underside. this pad provides a low thermal-resistance path for heat transfer into the pcb. this low thermally resistive path carries a majority of the heat away from the ic. the pcb is effectively a heatsink for the ic. the exposed pad should be connected to a large ground plane for proper thermal and electrical performance. the minimum size of the ground plane is dependent upon many system variables. to create an efficient path, the exposed pad should be soldered to a thermal landing, which is con - nected to the ground plane by thermal vias. the thermal landing should be at least as large as the exposed pad and can be made larger depending on the amount of free space from the exposed pad to the other pin landings. a sample layout is available on the MAX16993 evaluation kit to speed designs. pcb layout guidelines careful pcb layout is critical to achieve low switching losses and clean, stable operation. use a multilayer board whenever possible for better noise immunity and power dissipation. follow these guidelines for good pcb layout: 1) use a large contiguous copper plane under the device package. ensure that all heat-dissipating components have adequate cooling. 2) isolate the power components and high-current path from the sensitive analog circuitry. this is essential to prevent any noise coupling into the analog signals. 3) keep the high-current paths short, especially at the ground terminals. this practice is essential for stable, jitter-free operation. the high-current path comprising of input capacitor, high-side fet, inductor, and the output capacitor should be as short as possible. 4) keep the power traces and load connections short. this practice is essential for high efficiency. use thick copper pcbs (2oz vs. 1oz) to enhance full-load efficiency. 5) the analog signal lines should be routed away from the high-frequency planes. this ensures integrity of sensitive signals feeding back into the device. 6) use a single ground plane to reduce the chance of ground-potential differences. with a single ground plane, enough isolation between analog return signals and high-power signals must be maintained. MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
maxim integrated 23 typical application circuit bias pv1 bias vbatp 2.2f bst1 0.1f vsup dh1 1f lx1 MAX16993 gnd cs1 out1 0.1f 220f bias fb1 bias en2 bias sync csel1 ssen gnd ep v out1 v out1 bias vbatp v out1 (5v, 5a) 47f 20pf 47f pv3 lx3 10f 0.6h v out1 pgnd3 out3 pv 1f vsup reset1 47pf 4.7nf 0.1f fb1 d2 d1 0.1f 0.1f 47f 47f 47f 47f n1 dl1 n2 2.2h 22m? 40k? 10? en1 100k? 5.1k? 5.1k? reset1 err reset2 reset2 reset3 en3 reset3 err sync 100k? v out3 (1.2v, 3a) 10k? 20k? 47f 3.3pf 47f pv2 lx2 10f 1h v out1 pgnd2 out2 v out2 (3.3v, 3a) 75k? 24k? MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
maxim integrated 24 selector guide ordering information note: insert the desired suffix letter (from the selector guide) into the blank to indicate buck switching frequency, active time - out period, fixed or adjustable output voltages, maximum output current, and sync functionality. / v denotes an automotive qualified part. + denotes a lead(pb)-free/rohs-compliant package. * future product contact factory for availability. ** ep = exposed pad/side-wettable flanked package. package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. option buck 1 buck 2 buck 3 sync fixed output voltage (v) f sw1 divide ratio from f sw active timeout period (ms) fixed output voltage max output current (a) active timeout period (ms) fixed output voltage max output current (a) active timeout period (same as buck 2) (ms) a 3.3/5.0 5 3.9 adj 3.0 3.9 adj 3.0 3.9 input b 3.3/5.0 5 3.9 3.15v 1.5 3.9 1.8v 1.5 3.9 input c 3.3/5.0 5 1.9 adj 1.5 1.9 adj 1.5 1.9 input d* 3.3/3.15 2 3.9 1.35v 3.0 3.9 1.2v 1.5 3.9 input e 3.3/5.0 5 3.9 3.30v 1.5 3.9 1.5v 1.5 3.9 input part temp range pin-package MAX16993agj_/vy+ -40c to +125c 32 tqfn-ep** package type package code outline no. land pattern no. 32 tqfn-ep g3255y+1 21-0563 90-0361 MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters www.maximintegrated.com
? 2013 maxim integrated products, inc. 25 revision history revision number revision date description pages changed 0 5/13 initial release maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifcations without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. MAX16993 step-down controller with dual 2.1mhz step-down dc-dc converters for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.

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